FIG. 5 is a cross-sectional view of main portions of a semiconductor device equipped with a conventional MIS capacitive element. This semiconductor device comprises a substrate on which complementary MOS (CMOS) devices (not shown) are fabricated. This structure comprises the p-type silicon substrate 50 having a region over which the MIS capacitive element is to be formed. An n-type epitaxial layer 51 is formed in this region over the p-type substrate 50. A LOCOS oxide film 52 is formed on the surface of the epitaxial layer 51 so as to surround both a region in which the bottom electrode of the MIS capacitive element is to be formed and a region in which a contact is to be formed. An n-type doped layer 53a for the bottom electrode of the MIS capacitive element and an n-type doped layer 53b for the contact are formed in and on the epitaxial layer 51 surrounded by the LOCOS oxide film 52.
A silicon nitride (SiN) film 54 and a boro-phosphosilicate glass (BPSG) 55 are successively laminated on the LOCOS oxide film 52 so as to cover the surface of the epitaxial layer 51. In this structure, an oxide film 56 is interposed between the n-type doped layer 53b and the SiN film 54.
Those portions of the BPSG film 55 which are located just above the n-type doped layer 53a are removed, thus forming windows 55a. An aluminum (Al) electrode 57a (first MIS terminal) is formed as a top electrode over the SiN film 55 inside the windows 55a. The first MIS terminal 57a is formed over the n-type doped layer 53a via the SiN film 54, whereby an MIS capacitor 60 is formed. Contact holes 58 in communication with the n-type doped layer 53b are formed in the oxide film 56, in the SiN film 54, and in the BPSG film 55 which are located over the n-type doped layer 53b. An aluminum (Al) electrode (second MIS terminal) 57b is formed over the BPSG film 55 so as to fill in the contact holes 58. Thus, a contact is formed.
The circuit of the above-described conventional semiconductor device is shown in FIG. 6. A parasitic junction capacitance 61 formed between the n-type epitaxial layer 51 and the p-type Si substrate 50 shown in FIG. 5 exists between a substrate terminal 50a and the second MIS terminal 57b. Generally, the impedance Z of an RC series circuit decreases as the capacitance C is increased, as given by EQU Z={R.sup.2 +(1/.omega.C).sup.2 }.sup.1/2
where R is a resistance and .omega. is an angular velocity.
Accordingly, if the CMOS devices (not shown) formed on the substrate on which the MIS capacitor 60 is also formed operate, and if digital signals are transmitted to the substrate terminal 50a from the CMOS devices, then the digital signals pass through the parasitic junction capacitance 61 and go to the second MIS terminal 57b, as indicated by the arrow. As a result, the digital signals, or noises, enter a separate circuit connected with the MIS capacitive element, creating a crosstalk.